The present invention relates to data management. More specifically, the present invention relates to methods and apparatuses for managing large amounts of data, for example, in storage area networks and mainframe I/O environments.
The demands for managing large amounts of data have steadily increased in recent years and are expected to continue to increase in the future. For example, large organizations such as airlines and financial institutions require continuous, reliable, around-the-clock access to their xe2x80x9cmission criticalxe2x80x9d data. Temporary interruptions in the accessibility to this data, or the loss of portions of this data, can be catastrophic to such organizations. Complicating the management task, many organizations have an enormous and growing amount of mission critical data (e.g., many terabytes). Much of this data is managed by mainframe-based computer systems.
FIG. 1 shows a block diagram of an exemplary prior art computing system 100, which is described here to illustrate common management tasks and associated problems. System 100 includes two mainframe computers 110A, 110B, three direct access storage devices (DASDs, also known as xe2x80x9ccontrol unitsxe2x80x9d) 120A, 120B, 120C, and a director 150. The various components communicate with one another via xe2x80x9cpoint-to-pointxe2x80x9d communication links 160, 162, 164, 166, 168, 170, and 172 according to a defined protocol. The common protocol is the ESCON protocol, also known as the SBCON protocol (hereinafter, collectively called xe2x80x9cESCONxe2x80x9d).
In this exemplary system, port 114A of computer 110A is coupled to port 122B of control unit 120B via link 162. Port 112B of computer 110B is coupled to port 124B of control unit 120B via link 164. Port 114B of computer 110B is coupled to a port (not shown) of director 150 via link 166. Port 126B of control unit 120B is coupled to another port (not shown) of director 150 via link 168. Port 124C of control unit 120C is coupled to a port (not shown) of director 150 via link 170. In each case, the physical link and protocol are ESCON compliant. Finally, port P1 of control unit 120A is coupled to port P2 of control unit 120B via a proprietary communication link 172, in which the physical link is ESCON but which is used to carry proprietary commands and data, for example, to implement certain xe2x80x9cextended functionsxe2x80x9d (more below). For convenience of illustration, each computer 110A, 110B is illustrated as including two ESCON ports 112, 114.
In the illustrated embodiment, the mainframe computers are IBM S/390s. Exemplary IBM S/390 mainframe computer may include between sixteen to 256 ESCON communication ports.
Each exemplary DASD control unit 120, for ease of description, is shown as including three ESCON communication ports 122, 124, 126, and optionally additional private links P1, P2, though a typical DASD control unit may include between 2 and 64 ESCON ports. The illustrative DASD control units 120 include a main memory 130, a controller 132, a persistent storage 134, and three memory buffers 123, 125, 127, each buffer being associated with a corresponding ESCON port. Each port can write data into, and read data out of, its associated buffer. The controller 132 can write data into, and read data out of, all of the buffers or move data to or from persistent storage 134 via an internal system bus 136.
A director 150 improves connectivity in a storage network by allowing one mainframe computer port to connect to two or more control units.
As mentioned above, the various components may communicate using the ESCON protocol. Under ESCON, the components communicate according to xe2x80x9cchainsxe2x80x9d of one or more channel command words (CCWs). Each CCW, in turn, is communicated in three phases: a xe2x80x9ccommand phase,xe2x80x9d a xe2x80x9cdata phase,xe2x80x9d and a xe2x80x9cstatus phasexe2x80x9d with each phase using a known vocabulary of messages. During each phase, information is transmitted as xe2x80x9cframes,xe2x80x9d which are 1 kilobyte or less in size and include control (or header) and data (or payload) portions. A given phase may involve known flow control and/or handshaking and may involve many frames. For example, the protocol permits 64 kilobyte transfers, which could require 64 frames during the data phase. The data phase uses a flow control technique in which an initiator expresses a desire to transmit or read a certain amount of data (e.g., in a prior write command), and the receiver replies with a data request message indicating the size of data that may be sent by the transmitter and received by the receiver. A series of such requests may be needed to transfer the entire xe2x80x9cexchange.xe2x80x9d
The I/O protocols rely on a concept of virtual links connecting xe2x80x9cvirtual mainframe machinesxe2x80x9d with xe2x80x9cvirtual control units. Some of the I/O protocols, which are connection oriented, like ESCON and SCSI, allow only one connection to be active at any moment in time, while others may actually frame multiplex the information among the various virtual links. Virtual links are effectively identified by the frame header information specifying both physical and logical addresses, and the components can detect virtual connections and disconnections from analyzing specific bits in certain frames.
As alluded to above, commercially available control units offer xe2x80x9cextended functions.xe2x80x9d Extended functions implement features above and beyond basic device operations like read or write. (The actual functions implemented by a device are defined in the device specification, such as a specification of a control unit.) For example, two popular extended functions are known as xe2x80x9cconcurrent copyxe2x80x9d and xe2x80x9cremote copy,xe2x80x9d which are used, respectively, for maintaining backup copies or for xe2x80x9cmirroringxe2x80x9d data to other storage as it is written to its target. Known extended functions operate at a physical level of addressing (e.g., volume numbers and tracks) as opposed to operating at the logical level (e.g., files or the like). Referring back to FIG. 1, a control unit may perform back-up to another disk controlled by another control unit by using a dedicated ESCON link 172, connecting the two control units. Proprietary software (sometimes referred to as firmware), executing on the control units, performs the necessary operations over the link 172 to send the data to be backed up from one control unit to another.
In the above approach to mirroring, data is effectively written to the control units sequentially, first to the primary control unit and then from the primary control unit to the control unit doing the mirroring. This introduces delay and complication as the data is written between the control units. The backup approach is also sequential. These approaches require dedicated communication links 172 that cost port connections on the control units.
Moreover, because prior art extended functions are built using proprietary embedded software (also known as xe2x80x9cfirmwarexe2x80x9d) to and between control units, third parties cannot practically create additional functions for the control units. To date, the extended functionality is largely limited to homogenous systems of control units. That is, the extended functions generally do not work when control units from different manufacturers are involved in a network.
Clustering is similar to mirroring in that some data is effectively mirrored to storage associated with another processor. However, rather than mirroring information in case a subsequent failover or switchover to another storage proves necessary, clustering usually involves mirroring (or replicating) only specific information so that the processors may act collaboratively and in distributed fashion.
The inventions provides devices, systems, and methods of replicating and manipulating I/O information to improve efficiency and functionality. Preferably, the invention intercepts I/O information as it is transmitted between a computer (e.g., mainframe) and storage system (e.g., DASD storage controller).
Under certain aspects of the invention, an intelligent splitter device includes a buffer memory and at least three input/output (I/O) ports. Each port includes logic for transmitting and receiving information on an associated input/output (I/O) communication link, and each port is in electrical communication with the buffer memory. Control logic controls each port to write I/O data received from its respective I/O communication link into a portion of the buffer memory associated with that port. The control logic also controls each port to transmit data onto its respective I/O communication link by reading data from the buffer memory at selectable buffer memory locations, including locations associated with one of the other ports.
Under another aspect of the invention, the control logic can create both control and data frames. These frames may be created independently of any of the streams received by the intelligent splitter device.
Under other aspects of the invention, an intelligent splitter device communicates according to a frame-based I/O protocol in which each frame includes a header component and a payload component. The device includes a buffer memory and at least three input/output (I/O) ports. Each port has logic for transmitting and receiving information on an associated input/output (I/O) communication link, and each port is in electrical communication with the buffer memory. Control logic controls each port to write I/O data received from its respective I/O communication link into a portion of the buffer memory. And the control logic further includes logic to analyze a received frame and in response thereto create and transmit a modified version of the received frame on one of the I/O ports. The modified version of the frame includes a modification to at least one of the header component and the payload component of the received frame.
Under other aspects of the invention, an intelligent splitter device is used for communicating according to a multiphase I/O protocol having a command phase, a data phase, and a status phase in which the data phase has at least one data frame. The splitter includes a buffer memory and at least three input/output (I/O) ports. Each port has logic for transmitting and receiving information on an associated input/output (I/O) communication link, and each port is in electrical communication with the buffer memory. Control logic causes at least two of the ports to transmit in parallel data phase information.
Under another aspect of the invention, an intelligent splitter device is used for communicating according to a multiphase I/O protocol having a command phase, a data phase, and a status phase, in which the data phase comprises at least one data frame. The splitter includes a buffer memory and at least three input/output (I/O) ports. Each port has logic for transmitting and receiving information on an associated input/output (I/O) communication link, and each port is in electrical communication with the buffer memory. Control logic causes at least one port to transmit control phase information stored in the buffer. In parallel therewith, the control logic also causes at least one other port to transmit a modified version of the control phase information that is transmitted on the first port.
Using the above aspects, I/O information can be received on a first port of the communication device having at least three ports. The communication device can transmit the I/O information received on the first port to a second port of the communication device, and the communication device can transmit a modified version of the I/O information received on the first port to a third port of the communication device.
Moreover, I/O information can be received on a first port of the communication device, and the communication device can transmit a modified version of the information to one of the second and third ports of the communication device. Or, at least selected I/O information can be cached in the communication device, and I/O information can be received on a first port of the communication device. The received I/O information can be analyzed to determine physical address data of the I/O information, and the cached I/O information can be transmitted on the first port if the received information hits the cache. The received information can be transmitted on one of the second and third ports if the received information misses the cache.
Under another aspect of the invention, an intelligent splitter system includes an I/O device and a host system. The I/O device includes input/output (I/O) port logic for transmitting and receiving information on at least three I/O communication links according to a standardized I/O protocol. Under the protocol I/O operations may be requested on storage locations identified by physical address information. The I/O device further includes extended function logic that cooperates with the port logic to perform at least one extended function not specified in the standardized I/O protocol. The at least one extended function operates in a physical address domain of physical addresses. The host system has a processor and memory storing processor-executable instructions to map logical storage object names to a physical address domain. It also stores instructions to configure the I/O device with a mapped physical address domain to enable the I/O device to perform the at least one extended function on the physical address domain corresponding to a mapped logical storage object name.
Under other aspect of the invention, a command can be received to perform an extended function on data identified by a logical object name. The logical object name can be mapped to a physical address domain, and a communication link in the I/O system can be monitored to determine if the link is carrying an I/O operation in the mapped physical address domain. If an I/O operation is being carried on the link within the mapped physical address domain, that operation can be intercepted and the extended function identified in the received command can be performed.
Under another aspect of the invention, I/O information is received from one of the two communication links into a first multi-port device having a processor and memory. The memory has instructions to determine if I/O information received on the link is within a first predefined set of I/O operations, and the first multi-port device is connected to a first storage system. I/O information is also received from a second of the two communication links into a second multiport device having a processor and memory. This memory also stores instructions to determine if I/O information received on the link is within a second predefined set of I/O operations, and the second multi-port device is connected to a second storage system. If the received I/O information on the one communication link is within the first predefined set of I/O operations, the received I/O information is sent to the first storage device and an I/O operation is sent to a port of the second multi-port device. If the received I/O operation is not within the predefined set, the received information is sent to the first storage system. Similar actions to the above take place with respect to the second link.